Spin Torque Transfer Magnetic Random Access Memory, STT-RAM, is a second generation MRAM technology that may offer the advantages of the first generation MRAM without the drawbacks of poor scalability and high write current. Conventional STT-RAM is desired to combine the fast read and write speed of SRAM, the capacity and cost benefits of DRAM, and the non-volatility of Flash (zero standby power), coupled with essentially unlimited endurance (for example greater than 1015 cycle). As described below, STT-RAM uses a bi-directional current to write data. Such write operations may be performed without assistance from magnetic field, heat, or other sources of energy. Consequently, STT-RAM may have the lowest writing energy of emerging memory technologies
For example, FIGS. 1-3 depict portions of a conventional spin transfer torque magnetic random access memory (STT-RAM). FIG. 1 depicts a small portion of the STT-RAM 1 including a storage cell 10. FIG. 2 depicts the bit line sensing scheme, while FIG. 3 depicts a common source amplifier 50 used in connection with the memory 1. The conventional STT-RAM 1 utilizes spin transfer as a mechanism for switching the state of the magnetic storage cell. The conventional STT-RAM 1 includes a conventional magnetic storage cell 10 including a magnetic element 12 and a selection device 14. The selection device 14 is generally a transistor such as a NMOS transistor and includes a drain 11, a source 13, and a gate 15. Also depicted are a word line 16, a bit line 18, and source line 20. The word line 16 is oriented perpendicular to the bit line 18. The source line 20 is typically either parallel or perpendicular to the bit line 18, depending on specific architecture used for the conventional STT-RAM 1. The bit line 18 is connected to the magnetic element 12, while the source line 20 is connected to the source 13 of the selection device 14. The word line 16 is connected to the gate 15.
The conventional STT-RAM 1 programs the magnetic memory cell 10 by driving a bi-directional current through the cell 10. In particular, the magnetic element 12 is configured to be changeable between high and low resistance states by a current flowing through the conventional magnetic element 12. For example, the magnetic element 12 may be a magnetic tunneling junction (MTJ) or other magnetic structure that may be written using the spin transfer effect. Typically, this is achieved by ensuring that the magnetic element 12 has, for example, a sufficiently small cross-sectional area as well as other features desirable for switching using the spin transfer effect. When the current density is sufficiently large, the current carriers driven through the magnetic element 12 may impart sufficient torque to change the state of the magnetic element 12. When the write current is driven in one direction, the state may be changed from a low resistance state to a high resistance state. When the write current is passes through the magnetic element 12 in the opposite direction, the state may be changed from a high resistance state to a low resistance state.
During write operations, the word line 16 is high and turns on the selection device 14. The write current flows either from the bit line 18 to the source line 20, or vice versa, depending upon the state to be written to the magnetic memory cell 10. During read operations, the column decoder 22 selects the desired bit lines 18. A row decoder (not shown in FIG. 2 also enables the appropriate word line(s) 16. Thus, the word line 16 is high, enabling the selection device 14. Consequently, a read current flows from the bit line 18 to the source line 20. In addition to the read current (Idata in FIG. 2) flowing through the cell being read, reference currents are also driven through reference resistors Rref0 and Rref1. The output signals are provided to a sense amplifier, such as the conventional sense amplifier 50 shown in FIG. 3.
Because the magnetic element 12 is programmed by a current driven through the magnetic element 12, the conventional STT-RAM 1 may have better cell scalability and lower write current without suffering from the problem of write disturbance to the neighboring memory cells and smaller cell size for high memory density.
Although the conventional STT-RAM 1 functions, one of ordinary skill in the art will readily recognize that the STT-RAM 1 is still desired to be improved. More specifically, it is desirable to provide an STT-RAM that is scalable and has sufficiently fast access times to continue development as a next-generation nonvolatile memory.